Demand concerns ease, but production yields and advanced packaging remain hurdles for 16-layer adoption
Nvidia's Vera Rubin AI platform is expected to rely largely on 12-layer high-bandwidth memory chips, easing demand concerns for SK hynix and Samsung Electronics as the two Korean chipmakers advance 16-layer technology amid growing challenges in advanced packaging.
Market researcher Counterpoint Research said Friday that most Rubin-based products will likely use 12-layer HBM4, the sixth generation of high-bandwidth memory, rather than the eight-layer configuration that had been rumored in the industry.
The outlook challenges speculation that Nvidia had asked memory suppliers to reduce the number of stacked DRAM dies from 12 to eight, raising concerns that lower HBM requirements could free up production capacity for conventional DRAM and ease pressure on memory prices.
Counterpoint's latest assessment also marks a shift from its August report, which had pointed to Nvidia adopting an eight-layer HBM4 variant for Rubin.
The stakes extend beyond HBM itself. Producing high-performance chips can consume more than three times the wafer capacity required for conventional DRAM, meaning sustained AI demand could keep standard memory supplies tight even as chipmakers expand production.
The outlook comes as SK hynix and Samsung pursue higher-capacity HBM4 products, though the move from 12 to 16 layers has yet to translate into widespread commercial adoption.
SK hynix unveiled its 48-gigabyte, 16-layer HBM4 at CES in Las Vegas in January, offering one-third more capacity than its 36GB, 12-layer version. The company began mass supplying HBM4 to major customers in the second quarter and has since expanded production.
A September report by supply-chain tracker Silicon Analysts suggested that SK hynix had begun volume shipments of 16-layer HBM4 for Rubin, but the company has not publicly confirmed those deliveries.
At a Taiwan Semiconductor Manufacturing Co. technology conference later that month, SK hynix displayed a Vera Rubin superchip equipped with its 12-layer, 36GB HBM4, while showcasing the 16-layer version separately alongside other next-generation memory products.
The display underscored a distinction between having higher-capacity chips ready for customers and securing their use in commercial AI systems.
Samsung, meanwhile, has been shipping commercial HBM4 products since February, with its 12-layer lineup offering capacities of up to 36GB.
During its fourth-quarter earnings call in January, the company said demand for 16-layer HBM4 remained limited and that large-scale commercialization was not immediately necessary. However, its 16-layer stacking technology was ready for mass production should customer requirements change.
Samsung is also developing hybrid copper bonding technology designed to support memory stacks of 16 layers or more while reducing thermal resistance, a growing concern as manufacturers pack more DRAM dies into each chip.
Yet the competition is not simply about how many layers suppliers can stack.
HBM chips must be integrated with GPUs through advanced packaging processes, including TSMC's chip-on-wafer-on-substrate technology. Even with sufficient memory production, limited packaging capacity could constrain the supply of completed AI accelerators.
SK hynix has been working with TSMC to optimize the integration of its HBM products with advanced packaging, reflecting the growing importance of coordination between memory makers and foundries.
"If Rubin continues to rely mainly on 12-layer HBM4, the push for 16-layer chips is less about increasing near-term shipments than preparing for the higher memory capacity future AI systems will require," an industry source said on condition of anonymity.
"Being first to develop 16-layer technology matters less than achieving the yields and packaging compatibility customers actually need. The pace of supply expansion will ultimately depend on how well memory makers' capabilities align with TSMC's packaging capacity."
yeeun@heraldcorp.com